Directory of RSS feeds
Statistics

RSS feeds in the directory: 2816

Added today: 0

Added yesterday: 0

Culture / Music

Basics of electroacoustics

Understand the basics of sound reproduction.

Found 18 items

Consider the work of reversible registers on the example of two IMS. Reversible register KM555IR11 (Fig.25.9) implements four modes of operation, namely storing four-digit Ko-Yes, the left shift code, shift code to the right, parallel input and output code. the Modes of operation are specified two-digit code supplied to the control inputs S0, S1 Fig. 25.9. Reversible case . Modes of operation of the register for certain values of the signals at the inputs S0, S1 indicated in table 25.1 . table 25.1 in the Modes register the Parallel input information from inputs D1 – D4 occurs at the edge of the clock pulse at input C. thus inverted the input R must be filed by a logical 0 and the status of the inputs VR and VL are arbitrary. Shift of information in the...

Consider three integrated circuits of the parallel registers (Fig.25.8). Chip 530IR18. The register is designed to store six-digit word that is written and read in parallel code. The entry code is synchronous at the clock edge and when the voltage of the logical ports 0 and inverted input L. If the logical 1 on Ho L de code entry is prohibited and the action of input signals on the Q moves is not reflected. the Chip 530IR20. The register is a couple-regrettably two-channel multiplexer, driven by the entrance of WS. Under the action of a logic 0 at the entrance to WS by the front of the clock pulse the outputs Q record information from the inputs DA, under the action of logic 1 inputs DB. Fig. 25.8. Parallel registers Chip K555IR22. The register is designed...

Consider the work of the shift registers in the example of chip K155IR1 (Fig. 25.5). The operating mode register is set by the signal level at input L. Input sequential code, and shift it to the right is performed when L = 0. The input information is input to the VR and the clock pulses to the input of C1. A right shift by one digit occurs under the action of the slice clock pulse. Information after four clock pulses can be read from the outputs Q1 – Q4. Fig. 25.5. IC K155IR1 operating mode register is set by the signal level at input L. Input sequential code, and shift it to the right is performed when L = 0. The input information is input to the VR and the clock pulses to the input of C1. A right shift by one digit occurs under the action of the slice...

Reversible counters can operate in the addition mode and the subtraction mode. As can be seen from Fig. 24.1, 24.3, to change mode you need to connect or direct or inverted output of the previous trigger that is part of the counter to the T-input of the next. If the time period T will go To pulses when operating in the counter mode summation and N pulses during the operation of the counter in the subtraction mode, the counter state is equal to K–N (provided that the number of pulses K and N can uniquely be calculated by the meter). the Number of K–N can be both positive and negative. During the implementation of the processing devices, it is often necessary to know the sign of the number, obtained when applying different numbers of pulses. For this it is...

Consider counters K155IE2 and K155IE5. Graphic symbols of counters shown in Fig. 24.4. The counters are constructed as follows: each IP is the first of the triggers has a separate entrance C1 and direct access, the other three of the trigger are interconnected so that the way-out divider 8 in the IP type IE5 and 5 – in-style IP IE2. At the unity output of the first trigger input of C2 chains of the three triggers are formed four-digit counters, allowing them to make the division of the frequency of the input signal S1, respectively, 16 and 10. Fig. 24.4. Counters: a) K155IE5, b) K155IE2 Fig. 24.5. The structure of the counter IE5 Fig. 24.6. The structure of the counter IE2 IP two inputs R0 installation in 0, United under the scheme of "And". Reset (set to...

Counter – a device whose output produces the binary (BCD) code, defined by the number of received pulses. The counters are based on T-triggers. The main parameter of a counter – account module – the maximum number of individual signals which may be counted by the counter. Counters represent using ST (from the English. counter). Counters klassificeret: 1. According to the account module: - binary; - binary; - free permanent account module; - module variable account; 2. In the direction account: - summarizing; - subtractive - reversing; 3. According to the method of forming internal connections: - serial transfer; - parallel transport; - combined transport; - a ring. In a totalizer counter status (binary code on its output) with each pulse increasing by...

D-flip-flop (from the English. delay) remembers the input when you receive the clock. Speaking theoretically, D-flip-flop can be formed from any RS -, or JK flip-flops if their inputs simultaneously apply the mutually inverse signals. Storing information in the D-triggers is provided by synchronization, so all the real D-flip-flops have two inputs: D and information synchronization (Fig. 23.14). This trigger signal is input in the synchronization signal are recorded and transmitted to the output. Fig. 23.14. D-trigger as the information at the output remains unchanged until the arrival of the next sync pulse, the D-flop is also called a trigger with the memorization of information or trigger-latch. Conditional graphic designation of the D-flip-flop shown in...

JK flip-flop (from the English. jump and keep), different from the considered ruined RS-flip-flop that the advent of both information inputs (J and K) logical units (for direct inputs) leads to state change trigger. This combination of signals for the JK-flip-flop is not prohibited. In the rest of the JK flip-flop similar to an RS-trigger, and the role of S is played by the input J, and the role of the input R – input K. JK-triggers are implemented as in the form of a push-pull triggers (i.e. JK-triggers are synchronous). In Fig. 23.10 given symbol two-stage JK flip-flop. Fig. 23.10. JK flip-flop Complete the truth table of JK-flip-flop is similar to the truth table of RS-flip-flop, but does not have undefined state (Fig. 23.11). This table fair when you...

Call Trigger logic circuit with positive feedback, having two stable States – the unit and zero, which are denoted by respectively 1 and 0 (Fig.23.1, a). Each trigger is a ring of two inverters (Fig. 23.1, b, C). A trigger is a memory element posledovatelnosti logical devices in the diagrams it is denoted by T When power is applied to the result of transients arbitrarily one of the inverters installed in an isolated state, and the other is at zero. In the future, the state of the logic elements (LE) is stored as the output of one LE supports the condition of the other LE. A common such scheme is called the memory element or latch. the trigger Inputs are divided into information and control (auxiliary). This division is largely arbitrary. Information inputs...

In Fig. 22.11 shows a diagram to multiply two DVO-ary numbers: four-digit A = A4A3A2A1 and three-digit B = B3B2B1. Seven-digit product is formed by Paral-lennogo mnogiego multiplication for each bit of the multiplier logic elements 2I and addition of intermediate works with a shift of one digit - adder. While you have been supple mented with the following conditions: M2 = A2V1 + A1V2, similar to the results of Mi are formed by aggregated Here M is the carry bit from the previous column. The application LE AND the arithmetic operation of multiplication in this case is natural, since in one category, arithmetic, logical and multiplication subject to the General rules. The numbers in parentheses in chips refer to the example of multiplying two numbers A...

Comparison of multi-digit numbers based on checking the equality of numbers of numbers. Let the two numbers A3A2A1A0 and V3V2V1V0 . Compares A3 and B3 , B2 and A2 , B1 and A1 , B0 and A0 , the results of the comparison, the conclusion is: if match and third digits, and the second, first and zero, the number is the same. The truth table of the bitwise comparison is shown in Fig. 22.7. Fig. 22.7. The truth table of the bitwise comparison using the laws of algebra of logic it is possible to provide an expression output: Switching function F allows to implement a logical two-input NAND gates Exclusive OR. In Fig. 22.8 shows one embodiment of the implementation of the scheme comparison. Fig. 22.8. Schemes comparison of IP 155LP5 and 155LR3 it is Possible to...

Using the same adders can not only add, but also subtract binary numbers. Chip K555IM7 (Fig. 22.5 in) allows to sum or subtract four pairs of binary numbers received in the sequential code on inputs A and B. the Mode – summation or subtraction is set to inputs V the appropriate logic level. At V = 0 is implemented in the summation mode, when V = 1 – mode subtraction. Refresh the contents of the internal memories (triggers) and results in outputs S bitwise results is synchronous on clock edge at the input S. Provided in IM7 function is zero at R = 0 is the asynchronous operation: clear memory IP occurs regardless of the state of other inputs. In the calculation mode R = 1. The subtraction equivalent of the addition operation, the EU-whether the numbers...

Adder is called a combinational digital device designed to execute the operation arithmeti-IC of adding numbers represented in binary codes. Adders are used in the operations of summation and subtraction of numbers, but also form the basis of multiplication and division of numbers. The principle of treatment of digits of numbers after distinguish-coherent and parallel adders. In the serial adders the addition of numbers is done bitwise, after thus, in parallel – all bits are processed simultaneously. The number of insights distinguish polyommatini one-bit adders and multi-bit adders. Polyommatini and single-bit adders. Adding two single-digit binary numbers is characterized by the addition table (a truth table), which reflects the values of the input...

A Demultiplexer (DMX or DMS) is called functional unit, which provides the transmission of digital information received on one line to several output lines. Selection of output line is done with the help of signals on the address inputs. Thus, the demultiplexer performs the conversion, reverse the action of the multiplexer. Similarly, multiplexers, demultiplexers are complete and incomplete. Consider the operation of the demultiplexer have the future four outputs, the state of its inputs and outputs are given in the table (Fig. 21.6 a). From this table follows: Y0 = D(A0A1); Y1 = D(A0A1); Y2 = D(A0A1); Y3 = D(A0A1). (21.2) ie realize such a device can, as shown in Fig. 21.6 b. To increase the number of outputs of the demultiplexer use the cascade connection...

The Multiplexer is a functional node that performs lausy connection (switching) of one of several WMOs-ing data to the output. The number of the selected entry corresponds to the code submitted to the address inputs of multiplexer. Similarly, decoders, multiplexers are complete and incomplete. The multiplexer has the information, the address inputs and, as a rule, allow (gate). The development chausie inputs used to extend the functionality of a multiplexer. They are used to increase the capacity of a multiplexer, synchronization with other nodes. The signals on the enable inputs can allow and can not allow you to connect a certain input to output, i.e., can block the action of the entire device. The multiplexers denoted as MUX (from the English...