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Culture / Music

Basics of electroacoustics

Understand the basics of sound reproduction.

Found 12 items

D-flip-flop (from the English. delay) remembers the input when you receive the clock. Speaking theoretically, D-flip-flop can be formed from any RS -, or JK flip-flops if their inputs simultaneously apply the mutually inverse signals. Storing information in the D-triggers is provided by synchronization, so all the real D-flip-flops have two inputs: D and information synchronization (Fig. 23.14). This trigger signal is input in the synchronization signal are recorded and transmitted to the output. Fig. 23.14. D-trigger as the information at the output remains unchanged until the arrival of the next sync pulse, the D-flop is also called a trigger with the memorization of information or trigger-latch. Conditional graphic designation of the D-flip-flop shown in...

JK flip-flop (from the English. jump and keep), different from the considered ruined RS-flip-flop that the advent of both information inputs (J and K) logical units (for direct inputs) leads to state change trigger. This combination of signals for the JK-flip-flop is not prohibited. In the rest of the JK flip-flop similar to an RS-trigger, and the role of S is played by the input J, and the role of the input R – input K. JK-triggers are implemented as in the form of a push-pull triggers (i.e. JK-triggers are synchronous). In Fig. 23.10 given symbol two-stage JK flip-flop. Fig. 23.10. JK flip-flop Complete the truth table of JK-flip-flop is similar to the truth table of RS-flip-flop, but does not have undefined state (Fig. 23.11). This table fair when you...

Call Trigger logic circuit with positive feedback, having two stable States – the unit and zero, which are denoted by respectively 1 and 0 (Fig.23.1, a). Each trigger is a ring of two inverters (Fig. 23.1, b, C). A trigger is a memory element posledovatelnosti logical devices in the diagrams it is denoted by T When power is applied to the result of transients arbitrarily one of the inverters installed in an isolated state, and the other is at zero. In the future, the state of the logic elements (LE) is stored as the output of one LE supports the condition of the other LE. A common such scheme is called the memory element or latch. the trigger Inputs are divided into information and control (auxiliary). This division is largely arbitrary. Information inputs...

In Fig. 22.11 shows a diagram to multiply two DVO-ary numbers: four-digit A = A4A3A2A1 and three-digit B = B3B2B1. Seven-digit product is formed by Paral-lennogo mnogiego multiplication for each bit of the multiplier logic elements 2I and addition of intermediate works with a shift of one digit - adder. While you have been supple mented with the following conditions: M2 = A2V1 + A1V2, similar to the results of Mi are formed by aggregated Here M is the carry bit from the previous column. The application LE AND the arithmetic operation of multiplication in this case is natural, since in one category, arithmetic, logical and multiplication subject to the General rules. The numbers in parentheses in chips refer to the example of multiplying two numbers A...

Comparison of multi-digit numbers based on checking the equality of numbers of numbers. Let the two numbers A3A2A1A0 and V3V2V1V0 . Compares A3 and B3 , B2 and A2 , B1 and A1 , B0 and A0 , the results of the comparison, the conclusion is: if match and third digits, and the second, first and zero, the number is the same. The truth table of the bitwise comparison is shown in Fig. 22.7. Fig. 22.7. The truth table of the bitwise comparison using the laws of algebra of logic it is possible to provide an expression output: Switching function F allows to implement a logical two-input NAND gates Exclusive OR. In Fig. 22.8 shows one embodiment of the implementation of the scheme comparison. Fig. 22.8. Schemes comparison of IP 155LP5 and 155LR3 it is Possible to...

Using the same adders can not only add, but also subtract binary numbers. Chip K555IM7 (Fig. 22.5 in) allows to sum or subtract four pairs of binary numbers received in the sequential code on inputs A and B. the Mode – summation or subtraction is set to inputs V the appropriate logic level. At V = 0 is implemented in the summation mode, when V = 1 – mode subtraction. Refresh the contents of the internal memories (triggers) and results in outputs S bitwise results is synchronous on clock edge at the input S. Provided in IM7 function is zero at R = 0 is the asynchronous operation: clear memory IP occurs regardless of the state of other inputs. In the calculation mode R = 1. The subtraction equivalent of the addition operation, the EU-whether the numbers...

Adder is called a combinational digital device designed to execute the operation arithmeti-IC of adding numbers represented in binary codes. Adders are used in the operations of summation and subtraction of numbers, but also form the basis of multiplication and division of numbers. The principle of treatment of digits of numbers after distinguish-coherent and parallel adders. In the serial adders the addition of numbers is done bitwise, after thus, in parallel – all bits are processed simultaneously. The number of insights distinguish polyommatini one-bit adders and multi-bit adders. Polyommatini and single-bit adders. Adding two single-digit binary numbers is characterized by the addition table (a truth table), which reflects the values of the input...

A Demultiplexer (DMX or DMS) is called functional unit, which provides the transmission of digital information received on one line to several output lines. Selection of output line is done with the help of signals on the address inputs. Thus, the demultiplexer performs the conversion, reverse the action of the multiplexer. Similarly, multiplexers, demultiplexers are complete and incomplete. Consider the operation of the demultiplexer have the future four outputs, the state of its inputs and outputs are given in the table (Fig. 21.6 a). From this table follows: Y0 = D(A0A1); Y1 = D(A0A1); Y2 = D(A0A1); Y3 = D(A0A1). (21.2) ie realize such a device can, as shown in Fig. 21.6 b. To increase the number of outputs of the demultiplexer use the cascade connection...

The Multiplexer is a functional node that performs lausy connection (switching) of one of several WMOs-ing data to the output. The number of the selected entry corresponds to the code submitted to the address inputs of multiplexer. Similarly, decoders, multiplexers are complete and incomplete. The multiplexer has the information, the address inputs and, as a rule, allow (gate). The development chausie inputs used to extend the functionality of a multiplexer. They are used to increase the capacity of a multiplexer, synchronization with other nodes. The signals on the enable inputs can allow and can not allow you to connect a certain input to output, i.e., can block the action of the entire device. The multiplexers denoted as MUX (from the English...

At the output of the encoder (encoder) is set to binary code corresponding to decimal number initiated data input. In the callout boxes using the letters of the CD (from the English. Soder). The encoder can be used to represent (encode) a decimal number binary code and for issuing the specific code (the value pre-selected) when you press the corresponding symbol. When this code system is notified that a specific key is pressed on the keyboard. Fig. 20.5. Eight-bit decoder Similarly, the decoders, the encoders are complete and incomplete. For a complete encoder the condition n = 2 N , where n is the number of inputs, N is the number of outputs. Fig. 20.6. IC 155ID9 Fig. 20.7. Pair ID9 with led indicators To convert the code to the keypad in a four-digit...

A Decoder is called a Converter of a binary n-bit code in a unitary position 2n-bit code, all bits of which, except one, are equal to zero. De encoders are complete and incomplete. the full decoder the condition N = 2n, where n is the number of inputs, N is the number of outputs. If the decoder uses a partial number of outputs, the decoder is called incomplete. So, for example, a decoder with 4 inputs and 16 outputs, will be complete and with only 10 outputs is incomplete. In a symbol decoder uses the letters DC (from the English. Decoder). the inputs of the decoders are denoted by their binary weights. In addition to information inputs of the decoder has one or more of the inputs work, denoted as E (Enable). If you have permission on this input, the...

Digital logic devices are divided into two classes: combinational and posledovatelnostyu. Combinational digital devices implement various conversions of binary digital signals on the basis of combinational logic functions. The output signals of the com-bination devices at any time is uniquely determined by the input signals occurring in this mo-ment of time. the main types of such devices include adders, decoders and encoders, converters of codes, multiplexers and demultiplexers, charts comparison, binary numbers, etc. the Second logical device contains the sequential Celestia diagrams or finite state machines. The sequence-ing device necessarily include memory elements. Week-ends signals posledovatelnosti devices are determined not only by the signals...