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A Decoder is called a Converter of a binary n-bit code in a unitary position 2n-bit code, all bits of which, except one, are equal to zero. De encoders are complete and incomplete.
the full decoder the condition
N = 2n,
where n is the number of inputs, N is the number of outputs.
If the decoder uses a partial number of outputs, the decoder is called incomplete. So, for example, a decoder with 4 inputs and 16 outputs, will be complete and with only 10 outputs is incomplete. In a symbol decoder uses the letters DC (from the English. Decoder).
the inputs of the decoders are denoted by their binary weights. In addition to information inputs of the decoder has one or more of the inputs work, denoted as E (Enable). If you have permission on this input, the decoder operates in the manner described, in its absence, all outputs are de-encoder passive.
Figure 20.1 shows the symbol decoder, which has two binary inputs and four outputs. The operation of this decoder is described as a Boolean function mi:
symbol decoder (a) and scheme of its implementation (b) From the analysis of these relations it follows that rassmatrivaet my decoder converts each two-digit binary number into a logical unit on the corresponding output. Such decoders are widely is-used in the output device of the digital information to display binary numbers in decimal form to define the address bus to the memory chips, etc.
a Functional diagram of a decoder made on the basis written above logic functions, shown in Fig. 20.1 b.
With the help of inverters included in the entrance decrypts the Torah, on the internal data bus decoder is formed a complete set of logical signals:
using element And form respective output signals. The described decoder is implemented on the chip KR531ID14, which consists of two 2x4 Converter, i.e. each decoder has two data inputs and four inverted output and an inverted enable input E (Fig. 20.2).
Fig. 20.2. IC KR531ID14
the Numbers on the input (1, 2) denote the weight of the digit binary numbers, and the numbers on the output (0, 1, 2, 3) determine the decimal number corresponding to the specified number at the entrance.
At logic 1 at the enable input, all outputs will also be logic 1. When activating the enable input, i.e. when E = 0, a logical 0 appears at the output of the decoder, the number of which corresponds to the decimal equivalent of a binary number, served on informational inputs.
as an incomplete decoder can cause a chip K555ID6 (Fig. 20.3).
Fig. 20.3. Decoder K555ID6
the Decoder has 4 direct entry, denoted by A1,A2,A4,A8(address) 10 and inverse outputs. Digits define decimal number corresponding to a given binary number on the inputs. Clearly, this decoder is incomplete.
value of the active level (zero) is the output number equal to the decimal number determined by the binary number at the input.
for Example, if all inputs are logical zeros, the output Y0 is a logical zero and the other outputs a logical unit.
If the input A2 logical unit, while the remaining inputs are logical zero, the output Y2 is a logical zero and the other outputs a logical unit.
If the input is a binary number greater than 9 (for example, all the inputs units, which corresponds to the binary number 1111 or decimal 15), then all outputs – logical unit.
Due to the presence of the enable input can increase the dimensionality of the decoders. So using 5 decoders 2x4, you can build deshifrator4h16 (Fig. 20.4).
Fig. 20.4. The 4x16 decoder
the Scheme works as follows. For example, if you input the number of 0100 (binary equivalent of decimal number 4) and if E = 0 logical 0 will appear only on the second (top) output of decoder DC1, and on all other outputs are logic 1.
This will lead to enhancement of only the decoder DC3 and aktiviziruyutsya (will be a logical 0) only the top output that will correspond to the decimal number 4.
When you input the number 1111 is activated, the decoder DC5 and the lower part of the output will be a logical 0, which will correspond to the decimal number 15.
Obviously, if you use two chips KR531ID14, i.e. four 2x4 decoder, it is possible to build a partial decoder.
Consider the principle of the extension to the bit decoders for example, the full four-digit decoder.
the Principle of operation and construction of an 8-bit DC next. Is separation of code desifriranje number in two parts of 4 digits, Junior X3,x2,X1,X0 older X7,X6,X5,X4.
the Code defined by the senior combination of variables determines the selection of one of sixteen decoders. For example, if the input code H7H6H5H4H3H2H1H0=11110010, the most significant four digits, entering the inputs DSY lead to signal a logical zero on 15-th output DSY as 11112 = 1510, therefore, translates into working mode DS15.
the little bits that simultaneously arrive at DS0...DS15, determine the excitation of the second DC output as 00102 = 210. The result is the sum 111100002 = 24010 and 00102 = 210, i.e. 111100102 =24210. The remaining outputs of all decoders are in the state of the logical unit.
the eight-bit decoder Circuit shown in Fig. 20.5.
the Decoder is one of the widely used logic devices. It is used to construct various combinational devices. This is because the output of the decoder produces all possible logical product of all input variables. Connecting to certain conclusions decoder logic element OR using a decoder with the open exit and realizing it "OR mounting", you can implement any logic function.
One of the applications of decoders – control of led indicators. Decoder ID9 designed to manage incomplete led matrix .
the Matrix consists of discrete LEDs, designed for direct current of 10 mA.
Decoders and encoders 23.01.2019 at 08:50