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A Demultiplexer (DMX or DMS) is called functional unit, which provides the transmission of digital information received on one line to several output lines. Selection of output line is done with the help of signals on the address inputs. Thus, the demultiplexer performs the conversion, reverse the action of the multiplexer. Similarly, multiplexers, demultiplexers are complete and incomplete. Consider the operation of the demultiplexer have the future four outputs, the state of its inputs and outputs are given in the table (Fig. 21.6 a). From this table follows: Y0 = D(A0A1); Y1 = D(A0A1); Y2 = D(A0A1); Y3 = D(A0A1). (21.2) ie realize such a device can, as shown in Fig. 21.6 b. To increase the number of outputs of the demultiplexer use the cascade connection of the demultiplexers. As an example (Fig. 21.7) we will look at creating demux 16 outputs (1→16) based demultiplexers with 4 outputs (1→4). In the presence of a tire on the address A0 and A1 zeros data input X connected to the top of the DMX output and depending on the state of the address buses A2 and A3 it can be connected to one of the outputs DMX1. Thus, when A2 = A3 = 0 the input X is connected to Y3. When A0 = 1 and A1 = 0 the input X is connected to DMX2, depending on the state of the A2 and A3 input is connected to one of the outputs Y4 → Y7, etc. Functions of the demultiplexers is similar to the functions of desif-radarov. The decoder can be thought of as demultiplex-COP, whose data input supports voltage outputs in the active state, and address inputs serve as inputs to the decoder. Therefore, the designation as decoders and demultiplexers are the same letter ID.
Fig.21.6. The state table of the demultiplexer (a) and its realization in logic elements (b)
Decoder type K155ID3 can be used as a demultiplexer, i.e., a functional unit combination, which allows to switch a binary signal of one of N channels. The number of the switched channel is determined by the address binary code. So, the combination of X3, X2, X1, X0 specifies the number of the output of the decoder, which can be switched with one of the inputs E1 or E2. For example, when applying E2=0 E1 information transmitted on the corresponding output of the decoder. The rest of the outputs are always in the state of the logical unit. So, when X3, X2, X1, X0 = 0101 information from input "D" is supplied to the fifth output of the decoder, and, if necessary, a second input of the Gating can be used to fetch the IP details of a decoder, for example to increase the number of switched channels. In this case, you can do the same as when increasing the bit-depth decoder. Use ID3 as a demultiplexer is illustrated in Fig. 21.8.
Fig. 21.7. The demultiplexer 16 outputs
Decoder type K555ID4 – two decoder (demultiplexer) with the joint information inputs DI and separate enabling inputs E and G. Moreover, the control logic enabling the inputs of one decoder differs from the control logic enabling inputs of another decoder. Thus, the upper decoder is enabled when E1 & E2 = 1, while lower in G1 & G2 = 1. This allows no additional cost to implement a single decoder 3×8. Conditional graphical notation is shown in Fig. 21.9, and Fig. 21.10, and shows how to enable the IP to implement the decoder 3×8.
Fig. 21.8. K155ID3 decoder as a demultiplexer
Fig. 21.9. IC K155ID4
Fig. 21.10. The use of IMS K155ID4 as:
a) decoder 3×8 b) demux 1×8
In this case, the combined inputs E2 and G1 are used to supply the older variable X2, which provides a choice of top or bottom decoder, and the combined inputs E1 and G2 is used as strobe input W. For the implementation of the demultiplexer 1x8 is the same as the incorporation of IP, however, the inputs E2 and G1 receiving input signal D and the binary code is the address and sets the number of dial-up channel. The scheme of inclusion of IP as demux 1×8 shown in Fig. 21.10 b.
When using CMOS technology it is possible to build bi-directional keys that have the ability to pass a current in both directions and transmit not only digital but also analog signals. This makes it possible to construct multiplexers-demultiplexers that can be used either as multiplexers or as demultiplexers. Multiplexers - demultiplexers are denoted as MX.
the multiplexer-demultiplexer K561KP1 (Fig. 21.11) contains two chetyrehochkovym multiplexer 4→1, which can be used as demultiplexers 1→4.
the Chip comprises one common inverted enable input (gate) and two common address input. When a logical 1 on the enable input disables the outputs from the information inputs and go into high-impedance state.
At activation of the enable input, i.e., when applying to a logical 0, connection is one of the information inputs (in accordance with the code on the address inputs) from the IC output. Since this condition occurs with bidirectional keys in CMOS transistors, the signal can be transferred from inputs to the output (mode multiplexer) and the output to the inputs (mode demultiplexer).
in addition, the transmitted signal can be both analog and digital. Among manufactured multiplexers - demultiplexers can be made such as K564KP2, K590KP1. Multiplexers-demultiplexers are part of the series K176, K561, K591, K1564.
Fig. 21.11. A bidirectional multiplexer - demultiplexer K561KP1