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Adder is called a combinational digital device designed to execute the operation arithmeti-IC of adding numbers represented in binary codes. Adders are used in the operations of summation and subtraction of numbers, but also form the basis of multiplication and division of numbers. The principle of treatment of digits of numbers after distinguish-coherent and parallel adders. In the serial adders the addition of numbers is done bitwise, after thus, in parallel – all bits are processed simultaneously. The number of insights distinguish polyommatini one-bit adders and multi-bit adders. Polyommatini and single-bit adders. Adding two single-digit binary numbers is characterized by the addition table (a truth table), which reflects the values of the input numbers A and b, the value of the resulting sum S and a carry value in the MSB of the R (Fig. 22.1).
Fig. 22.1. Truth table of half-adder
the Operation of the device that implements a truth table is described by the following equations:
S=A*B+A*B = A * B, P=A*B. (22.1)
Obviously, in relation to the column S implements the logical function "exclusive OR". A device that implements a table, called a half-adder, and it has the logical structure shown in Fig. 22.2.
Fig. 22.2. The logical structure of the half-adder (a) and its symbol (b)
Since the half-adder has only two inputs, it can be used to sum only the lower digit.
the summing of two multi-digit numbers for each category (except Junior) you must use the device having an additional carry-in input. Such a device (Fig. 22.3) are called a full adder and can be represented as the Union of two Polyommatus (RIRS – additional carry-in input). Indicate through the adder SM.
Fig. 22.3. The logical structure of a full adder (a) and its truth table (b)
Multibit adders. Connecting in a certain way polyommatini and full adders with each other, receive the device for performing the addition of multiple bit binary numbers.
as an example, consider a device to add two three-digit binary numbers A2A1A0 and V2V1V0, where A0 and B0 – significant bits of binary numbers (Fig. 22.4).
Fig. 22.4. Three-digit adder
the outputs S1 to S3 is generated code amount of numbers A2A1A0 and V2V1V0, and the output P3 of the carry signal to the next chip, since adding two three-digit binary numbers can get a four-digit number.
Considered the parallel adder is called a full adder.
In the form of integrated circuits are produced single-digit, two-digit and four-digit binary adders. For example, diagrams of adders by the industry (Fig. 22.5).
Fig. 22.5. IC adders: a) K155IM5, b) K555IM6 in) K555IM7
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