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JK flip-flop (from the English. jump and keep), different from the considered ruined RS-flip-flop that the advent of both information inputs (J and K) logical units (for direct inputs) leads to state change trigger. This combination of signals for the JK-flip-flop is not prohibited. In the rest of the JK flip-flop similar to an RS-trigger, and the role of S is played by the input J, and the role of the input R – input K. JK-triggers are implemented as in the form of a push-pull triggers (i.e. JK-triggers are synchronous). In Fig. 23.10 given symbol two-stage JK flip-flop.
Fig. 23.10. JK flip-flop
Complete the truth table of JK-flip-flop is similar to the truth table of RS-flip-flop, but does not have undefined state (Fig. 23.11). This table fair when you activate the sync input.
Fig. 12.11. The truth table of JK-flip-flop
For dynamic triggers is characterized by the blocking of information inputs at the time when the information is transferred to the output.
it Should be noted that in terms of response to input signals of the dynamic trigger fired when changing of the input signal from 1 to 0, similar to that considered two-stage trigger, although they differ in internal structure.
For direct dynamic inputs use the symbol shown in Fig. 14.2 (trigger edge), and for inverse dynamic input uses the symbol shown in Fig. 14.2, b (trigger on the falling edge).
For example, consider a chip K555TV9 (Fig. 23.12), which consists of two JK-flip-flop with dynamic control for synchronization input with inverted inputs asynchronous install R and S.
Fig. 23.12. IC K555TV9
When applying a logic 0 on the S input and a logic 1 at the input R trigger is established in a single state (Q = 1). When applied to the S input of logical 1, and logic 0 input R trigger set to the zero state (Q = 0). When S = R = 1 the trigger works as a synchronous JK-flip-flop, and triggered it when you change the signal on the trigger input from 1 to 0.
JK flip-flop is a universal flip-flop. The versatility of the JK-flip-flop lies in the possibility of implementing it on the basis of RS, T and D flip-flops. Conversion of JK flip-flop in RS, T, D-triggers shown in Fig. 23.13. Supply level of logical one "1" is performed either by connecting a resistor (about 1kOhm) connected to a +5 V or to the output of the free element AND, one input of which is connected to the housing.
Fig. 23.13. Implementation based on JK other types of triggers:
a) asynchronous RS-trigger, b) asynchronous T-flip-flop, q) synchronous T flip-flop d) D flip-flop
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