RSS feeds in the directory: 374
Added today: 0
Added yesterday: 0
D-flip-flop (from the English. delay) remembers the input when you receive the clock. Speaking theoretically, D-flip-flop can be formed from any RS -, or JK flip-flops if their inputs simultaneously apply the mutually inverse signals. Storing information in the D-triggers is provided by synchronization, so all the real D-flip-flops have two inputs: D and information synchronization (Fig. 23.14). This trigger signal is input in the synchronization signal are recorded and transmitted to the output.
Fig. 23.14. D-trigger
as the information at the output remains unchanged until the arrival of the next sync pulse, the D-flop is also called a trigger with the memorization of information or trigger-latch.
Conditional graphic designation of the D-flip-flop shown in Fig. 23.15.
Fig. 23.15. Conditional graphic designation of the D-flip-flop
D-trigger can also be equipped with additional inputs asynchronous setup. Thus, the chip K561TM2 (Fig. 23.16) represents two triggers with dynamic control inputs synchronization with asynchronous inputs the installation of R and S .
Fig. 23.16. IC K155TM2
When applied to the S input of logical 0 and input R is a logical 1, the trigger is established in a single state (Q = 1). When applied to the S input of logical 1 and input R is a logical 0 trigger set to the zero state. When S = R = 1 flip-flop works as a D-latch, repeating at the output Q the input D when exposed to positive edge on the sync input.
JK-triggers 05.09.2019 at 11:24
RS-triggers 05.09.2019 at 10:55
Peremezhaya device-based adders 05.09.2019 at 07:50
Comparison of binary numbers 05.09.2019 at 07:34
Subtraction of binary numbers 05.09.2019 at 06:33
The adders sum the binary numbers 19.02.2019 at 06:52
Demultiplexers 14.02.2019 at 08:14
Multiplexers 12.02.2019 at 08:37
Encoders 23.01.2019 at 11:59
Decoders 23.01.2019 at 09:01