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Consider the work of reversible registers on the example of two IMS. Reversible register KM555IR11 (Fig.25.9) implements four modes of operation, namely storing four-digit Ko-Yes, the left shift code, shift code to the right, parallel input and output code.
the Modes of operation are specified two-digit code supplied to the control inputs S0, S1
Fig. 25.9. Reversible case
. Modes of operation of the register for certain values of the signals at the inputs S0, S1 indicated in table 25.1 .
in the Modes register
the Parallel input information from inputs D1 – D4 occurs at the edge of the clock pulse at input C. thus inverted the input R must be filed by a logical 0 and the status of the inputs VR and VL are arbitrary.
Shift of information in the form of a consistently-th code, the input VR and VL were also committed under the influence of the fronts of clock pulses. The state of the inputs D, as well as one of VR or VL (depending on the shift direction) can be arbitrary. Reversible register KR1533IR24 shown in Fig. 25.10.
Fig. 25.10. Reversible register KR1533IR24
Register is designed to store eight-bit words, and convert the parallel code in serial, and Vice versa. Register functions the following synchronous modes: parallel input code sequential code input shift right serial input of the code shift to the left. Specifies the two-digit mode code acting on the inputs S1, S0 (table 25.2).
a Feature of the register is a bidirectional eight-bit data bus, the data transfer direction is set by the States of OE and S; the same mode is set to a third state outputs Z mode (high impedance state). The status bus, depending on the state of these inputs is given in table 25.3.
Fixing the shift code occurs on the edge of the pulse applied to input C on the inverse input R should be a logical 1 voltage. The reset register in the zero state is performed asynchronously by feeding inverted input R logic 0. In storage mode (S1 = S0 = logic 0) the write, shift code, and reset the register is impossible. When you enable the high impedance mode (OE1 = logical 1, input status, OE2, S1, S2 is indifferent) it is possible to produce parallel code entry, shift right or left, information storage and reset of the register.
Additional outputs Q1 and Q8 is designed for reading the serial code when moving it to the right or VLE-in. When the shift code to the left from the output of Q1 is read serial code youngest discharge forward in the shift code to the right output Q8 is read serial code most significant bit forward.
Parallel registers 17.03.2020 at 06:21
Shift registers 17.03.2020 at 06:01
Reversible counters 16.03.2020 at 11:30
. Counters 16.03.2020 at 08:59
Pulse counters 16.03.2020 at 06:41
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JK-triggers 05.09.2019 at 11:24
RS-triggers 05.09.2019 at 10:55
Peremezhaya device-based adders 05.09.2019 at 07:50
Comparison of binary numbers 05.09.2019 at 07:34